What is the frequency of ddr2 ram. Modern types of memory DDR, DDR2, DDR3 for desktop computers

Description

In addition to the division by bandwidth and capacity, the modules are divided by:

• the presence of an additional memory chip for the error correction code. Denoted by ECC characters, for example: PC2-6400 ECC;
• the presence of a specialized addressing chip - register.
  "Normal" modules are referred to as "non-registered" or "unbuffered". The register in buffered - "registered" - modules improves the signal quality of the command-address lines (at the cost of an additional delay cycle when accessing), which allows you to increase the frequencies and use up to 36 memory chips per module, creating modules increased capacity, which are commonly used in servers and workstations. Almost all currently produced DDR2 Reg modules are also equipped with ECC.
• the presence of an AMB (Advanced Memory Buffer) chip. Such modules are called fully buffered, denoted by the letters F or FB, and have a different key location on the module. This is a further development of the idea of ​​registered modules - Advanced Memory Buffer buffers not only address signals, but also data, and uses serial bus to the memory controller instead of parallel. These modules cannot be installed in motherboards designed for other types of memory, and the key position prevents this.

As a rule, even if the motherboard supports registered and unbuffered (normal memory) modules, modules different types(registered and unbuffered) cannot work together on the same channel. Despite the mechanical compatibility of the connectors, Registered memory simply will not start in motherboard, designed to use conventional (unbuffered) memory and vice versa. The presence / absence of ECC does not affect the situation in any way. All this applies to both conventional DDR and DDR-II.

It is categorically impossible to use Registered memory instead of conventional memory and vice versa. Without any exceptions. The only exception at present are dual-processor LGA1366 boards that work with both regular and Registered DDR-III, but you cannot mix the two types of memory in one system.

Advantages over DDR

• Higher bandwidth
• Generally lower power consumption
• Improved design to promote cooling

• Typically higher CAS latency (3 to 6)
• The resulting delays at the same (or even higher) frequencies are higher

DDR2 is gradually being replaced by DDR3.

see also

Literature

V. Solomenchuk, P. Solomenchuk PC iron. - 2008. - ISBN 978-5-94157-711-8

Notes

Links

Wikimedia Foundation. 2010 .

The component market is constantly updated with new developments and innovations with enviable regularity, which is why many users whose funds clearly do not allow them to acquire new hardware in a timely manner have doubts about the power and performance of their computer as a whole. At all times, the discussion of a lot of questions on technical forums about the relevance of their components never subsides. At the same time, questions concern not only the processor, video card, but even random access memory. However, despite all the dynamics of the development of computer hardware, the relevance of technologies of previous generations is not lost as quickly. This also applies to components.

DDR2 memory: from the first days on the market to the decline of popularity

DDR2 is the second generation of random access memory (from the English. Synchronous Dynamic random access memory - SDRAM), or, in the usual formulation for any user, the next generation of RAM after DDR1, which has become widespread in the personal computer segment.

Being developed back in 2003, the new type could fully gain a foothold on the market only by the end of 2004 - only at that time chipsets with DDR2 support appeared. Actively advertised by marketers, the second generation was presented as almost twice as powerful an alternative.

What stands out from the differences in the first place is the ability to operate at a much higher frequency, transmitting data twice in one clock cycle. On the other hand, the standard negative point of raising frequencies is an increase in the delay time during operation.

Finally, by the mid-2000s, the new type fundamentally infringed on the positions of the previous, the first, and only by 2010 was DDR2 significantly pressed out by the new DDR3 that replaced it.

Device Features

Distributed DDR2 RAM modules (colloquially referred to as "sticks") had some distinctive features and varieties. And although the new one for its time did not frankly strike with an abundance of variations, however, even external differences were immediately evident to any buyer at first sight:

• Single-sided/double-sided SDRAM module, on which chips are located on one or both sides, respectively.
• DIMM is today's standard form factor for SDRAM (synchronous dynamic random access memory, which is DDR2). Mass use in general purpose computers began in the late 90s, which was mainly facilitated by the appearance of the Pentium II processor.
• SO-DIMM is a short form factor SDRAM module designed specifically for laptop computers. Notebook SO-DIMM DDR2 dies had several significant differences from standard DIMMs. This is a module with smaller physical dimensions, lower power consumption and, as a result, a lower level of performance compared to the standard DIMM factor. An example of a DDR2 RAM module for a laptop can be seen in the photo below.

In addition to all the above features, it should also be noted the rather mediocre "shell" of the dice of those times - almost all of them, with rare exceptions, were then represented only by standard boards with microcircuits. Marketing in the computer hardware segment was just beginning to unwind, so there were simply no samples on sale with radiators of various sizes and designs familiar to modern RAM modules. Until now, they perform primarily a decorative function, rather than the task of removing the generated heat (which, in principle, is not typical of DDR RAM).

In the photo below, you can see what DDR2-667 RAM modules with a heatsink look like.

Compatibility Key

DDR2 memory in its design has an extremely important difference from the previous DDR - the lack of backward compatibility. In the samples of the second generation, the slot in the contact zone of the bracket with the RAM slot on the motherboard was already located differently, which is why it is physically impossible to insert a DDR2 die into a DDR slot without breaking one of the components.

Volume parameter

For mainstream motherboards (any motherboard for home/office use), the DDR2 standard could offer a maximum of 16 gigabytes. For server solutions, the volume limit reached 32 gigabytes.

It is also worth paying attention to one more technical nuance: minimum volume one dice is 1 GB. In addition, there are two more options for DDR2 modules on the market: 2Gb and 8Gb. Thus, in order to get the maximum possible supply of RAM of this standard, the user will have to install two 8 GB sticks or four 4 GB sticks, respectively.

Communication frequency

This parameter is responsible for the ability of the memory bus to pass as much information as possible per unit of time. A higher frequency value means more data can be transferred, and here DDR2 memory significantly outperformed the previous generation, which could operate in the range from 200 to 533 MHz maximum. After all, the minimum frequency of the DDR2 bar is 533 MHz, and the top copies, in turn, could boast of overclocking to 1200 MHz.

However, with the growth of the memory frequency, the timings naturally also increased, on which the memory performance not least depends.

About timings

Timing is the time interval from the moment the data is requested to the time it is read from the RAM. And the more the module frequency increased, the longer the RAM needed time to complete operations (not to enormous delays, of course).

The parameter is measured in nanoseconds. The most affecting performance is the latency timing (CAS latency), which is denoted as CL* in the specifications (any number can be specified instead of *, and the smaller it is, the faster the memory bus will work). In some cases, the timings of the bars are indicated by a three-character combination (for example, 5-5-5), however, the first number will be the most critical parameter - it always indicates the memory latency. If the timings are specified in a four-digit combination, in which the last value is strikingly larger than all the others (for example, 5-5-5-15), then this is the duration of the total duty cycle in nanoseconds.

An old man who does not lose shape

With its appearance, the second generation caused a lot of noise in computer circles, which provided it with considerable popularity and excellent sales. DDR2, like its predecessor, could transfer data on both slices, but a faster bus with data transfer capability significantly improved its performance. In addition, higher energy efficiency was also a positive point - at the level of 1.8 V. And if this hardly had any effect on the overall picture of computer power consumption, then it had a purely positive effect on the service life (especially with intensive iron work).

However, technologies ceased to be such if they did not develop further. This is exactly what happened with the advent of the next generation of DDR3 in 2007, the task of which was to gradually but surely push out the outdated DDR2 from the market. However, does this "obsolescence" really mean total incompetence with the new technology?

One on one with the third generation

In addition to traditional backward incompatibility, DDR3 introduced a number of several technical innovations in RAM standards:

• The maximum supported volume for serial motherboards has increased from 16 to 32 GB (at the same time, the indicator of one module could reach 16 GB instead of the previous 8).
• Higher data rates with a minimum of 2133 MHz and a maximum of 2800 MHz.
• Finally, the reduced power consumption standard for each new generation: 1.5 V versus 1.8 V for the second generation. In addition, two more modifications were developed based on DDR3: DDR3L and LPDDR3, consuming 1.35 V and 1.2 V, respectively.

Along with the new architecture, timings have also increased, but the drop in performance from this is offset by higher operating frequencies.

How does the buyer decide?

The buyer is not a development engineer; in addition to technical characteristics, the price of the product itself will be no less important to the buyer.

At the start of sales of a new generation of any computer hardware, its cost will usually be higher. The same new type of RAM first hits the market with a very large price difference compared to the previous one.

However, the increase in performance between generations in most applications, if not absent at all, is simply ridiculous indicators, clearly not worthy of large overpayments. The only right time to switch to a new generation of RAM is when its price tag drops to the level of the previous one (this always happens in the SDRAM sales segment, it was the same with DDR2 and DDR3, the same is now happening with DDR3 and the new DDR4). And only when the price of the overpayment between the last and the previous generation will be at the very minimum (which is adequate for a small increase in performance), then only in this situation can one think about replacing the RAM.

In turn, it is most rational for owners of computers with DDR2 memory to acquire a new type of RAM only with a thorough upgrade from the appropriate one that supports this newest type, and a new motherboard(and today it makes sense to upgrade to the level of components that support DDR4 memory: its current price is on a par with DDR3, and the increase between the fourth and second generation will be much more noticeable than between the third and second).

Otherwise, if such an upgrade is not planned by the user at all, then it is quite possible to get by with the same DDR2, the price of which is now relatively low. It will be enough just to increase, if necessary, the total amount of RAM with similar modules. The allowable memory limits of this type even today more than cover all the needs of most users (in most cases, it will be enough to install an additional DDR2 2Gb module), and the performance lag with the next generations is completely uncritical.

Minimum prices for RAM modules (only samples of verified brands Hynix, Kingston and Samsung are taken into account) may vary depending on the region of residence of the buyer and the store chosen by him.

In this article, we will look at 3 types of modern RAM for desktop computers:

• DDR- is the oldest type of RAM that you can still buy today, but its dawn has already passed, and this is the most old view RAM, which we will consider. You will have to find far from new motherboards and processors that use this type of RAM, although many existing systems use DDR RAM. The operating voltage of DDR is 2.5 volts (usually increases when the processor is overclocked), and is the largest consumer of electricity from the 3 types of memory we are considering.
• DDR2 is the most common type of memory used in modern computers. It's not the oldest, but it's not newest look random access memory. DDR2 is generally faster than DDR, and therefore DDR2 has a higher data transfer rate than the previous model (the slowest DDR2 model is equal in speed to the fastest DDR model). DDR2 consumes 1.8 volts and, like DDR, the voltage usually increases when the processor is overclocked.
• DDR3- fast and new memory type. Again, DDR3 is faster than DDR2, and thus the lowest speed is the same as the fastest DDR2 speed. DDR3 consumes less power than other types of RAM. DDR3 consumes 1.5 volts, and a little more when overclocking the processor

Table 1: Specifications RAM according to JEDEC standards

JEDEC- Joint Electron Device Engineering Council (Joint Engineering Council for Electronic Devices)

The most important characteristic on which memory performance depends is its bandwidth, which is expressed as the product of the system bus frequency and the amount of data transferred per cycle. Modern memory has a bus width of 64 bits (or 8 bytes), so the bandwidth of DDR400 memory is 400 MHz x 8 Bytes = 3200 MB per second (or 3.2 GB / s). Hence, another designation for this type of memory follows - PC3200. Recently, dual-channel memory connection is often used, in which its bandwidth (theoretical) doubles. Thus, in the case of two DDR400 modules, we will get the maximum possible speed data exchange 6.4 GB / s.

But on maximum performance memory is also affected by such important parameters as "memory timings".

It is known that the logical structure of the memory bank is two-dimensional array- the simplest matrix, each cell of which has its own address, row number and column number. To read the contents of an arbitrary array cell, the memory controller must specify the RAS row number (Row Adress Strobe) and the CAS column number (Column Adress Strobe), from which the data is read. It is clear that there will always be some kind of delay (memory latency) between the issuance of a command and its execution, and these very timings characterize it. There are many different parameters that determine timings, but four of them are most commonly used:

• CAS Latency (CAS) - the delay in cycles between the CAS signal and the actual output of data from the corresponding cell. One of the most important characteristics of any memory module;
• RAS to CAS Delay (tRCD) - the number of memory bus cycles that must pass after the RAS signal is given before the CAS signal can be sent;
• Row Precharge (tRP) - the time it takes to close a page of memory within one bank, spent on recharging it;
• Activate to Precharge (tRAS) - strobe active time. The minimum number of cycles between an activation command (RAS) and a precharge command (Precharge), which ends work on this line, or closes the same bank.

If you see the designations "2-2-2-5" or "3-4-4-7" on the modules, you can be sure that these are the parameters mentioned above: CAS-tRCD-tRP-tRAS.

The standard CAS Latency values ​​for DDR memory are 2 and 2.5 cycles, where CAS Latency 2 means that data will be received only two cycles after the Read command is received. In some systems, values ​​of 3 or 1.5 are possible, and for DDR2-800, for example, latest version The JEDEC standard defines this parameter in the range from 4 to 6 cycles, while 4 is an extreme option for selected "overclocker" microcircuits. RAS-CAS and RAS Precharge latency is typically 2, 3, 4, or 5 clocks, while tRAS is slightly longer, from 5 to 15 clocks. Naturally, the lower these timings (at the same clock frequency), the higher the memory performance. For example, a module with a CAS latency of 2.5 usually performs better than one with a latency of 3.0. Moreover, in a number of cases, memory with lower timings, even at a lower clock frequency, turns out to be faster.

Tables 2-4 provide general DDR, DDR2, DDR3 memory speeds and specifications:

Table 2: Common DDR Memory Speeds and Specifications

Table 3: Common DDR2 Memory Speeds and Specifications

Table 4: Common DDR3 Memory Speeds and Specifications

DDR3 can be called a newcomer among memory models. Memory modules of this kind are only available for about a year. The efficiency of this memory continues to grow, has only recently reached the JEDEC boundaries, and has gone beyond these boundaries. Today, DDR3-1600 (the highest speed of JEDEC) is widely available, and more manufacturers are already offering DDR3-1800). Prototypes of DDR3-2000 are shown on the modern market, and should go on sale at the end of this year - early next year.

The percentage of DDR3 memory modules entering the market, according to manufacturers, is still small, in the range of 1%-2%, which means that DDR3 has a long way to go before it can match DDR sales (still in the 12%-2% range). 16%) and this will allow DDR3 to get closer to DDR2 sales. (25%-35% according to manufacturers).

Now the current RAM standard is DDR4, but there are still many computers with DDR3, DDR2 and even DDR in use. Because of this RAM, many users get confused and forget what kind of RAM is used on their computer. This article will be devoted to solving this problem. Here we will tell you how to find out what kind of RAM is used on a computer DDR, DDR2, DDR3 or DDR4.

If you have the opportunity to open the computer and inspect its components, then you can get all the necessary information from the sticker on the RAM module.

Usually on the sticker you can find an inscription with the name of the memory module. This name begins with the letters "PC" followed by numbers, and it indicates the type of RAM in question and its throughput in megabytes per second (MB/s).

For example, if a memory module says PC1600 or PC-1600, then it is a first-generation DDR module with a bandwidth of 1600 MB/s. If the module says PC2-3200, then it is DDR2 with a bandwidth of 3200 MB/s. If PC3 is DDR3 and so on. In general, the first digit after the letters PC indicates the DDR generation, if this number is not present, then it is a simple first generation DDR.

In some cases, RAM modules do not indicate the name of the module, but the type of RAM and its effective frequency. For example, DDR3 1600 may be written on the module. This means that this is a DDR3 module with an effective memory frequency of 1600 MHz.

In order to correlate the names of modules with the type of RAM, and the bandwidth with the effective frequency, you can use the table that we give below.

Using special programs

If your RAM modules are already installed in the computer, then you can find out what type they are using special programs.

The easiest option is to use free program CPU-Z. To do this, launch CPU-Z on your computer and go to the "Memory" tab. Here, in the upper left corner of the window, the type of RAM that is used on your computer will be indicated.

Also on the "Memory" tab, you can find out the effective frequency at which your RAM is running. To do this, you need to take the value of "DRAM Frequency" and multiply it by two. For example, in the screenshot below, the frequency is 665.1 MHz, multiply it by 2 and get the effective frequency of 1330.2 MHz.

If you want to know what specific RAM modules are installed on your computer, then this information can be obtained on the "SPD" tab.

Here you can find out how many memory modules are installed, who their manufacturer is, at what frequencies they can operate, and much more.

Theoretical foundations and first results of low-level testing

DDR2 is a new memory standard approved by the Joint Electronic Device Engineering Council, which includes many manufacturers of chips and memory modules, as well as chipsets. Early versions of the standard were published already in March 2003, it was finally approved only in January 2004 and received the name DDR2 SDRAM SPECIFICATION, JESD79-2, revision A (). DDR2 is based on the well-known and proven DDR (Double Data Rate) technology. You can even say this: "DDR2 starts where DDR ends." In other words, the first DDR2 will operate at frequencies that are the limit for the current generation of DDR-400 memory (PC3200 standard, clock frequency 200 MHz), and its further versions will significantly surpass it. The first generation of DDR2 memory, already currently being produced by vendors such as, and, are its DDR2-400 and DDR2-533 varieties, operating at 200 MHz and 266 MHz, respectively. Next, a new generation of DDR2-667 and DDR2-800 modules is expected, although it is noted that they are unlikely to appear at all and, moreover, will become widespread even by the end of this year.

In fairness, it should be noted that DDR2 memory, as such, appeared quite a long time ago - of course, I mean the memory on video cards. However, this variation of DDR2 (called GDDR2) is actually special type memory designed specifically for the video card market and slightly different from the "desktop" version of DDR2, which is the subject of this review. general information

So, "desktop" DDR2-SDRAM is considered as an evolutionary replacement for the current generation of memory DDR. The principle of its operation is absolutely the same data transfer (at the level of the memory module) is carried out over a 64-bit bus on both parts of the clock signal (upward “front” and downward “cutoff”), which provides twice the effective data transfer rate in relation to its frequency. Of course, at the same time, DDR2 implements a number of innovations that make it possible to jump to much higher frequencies (and, consequently, higher bandwidth) and larger capacities of microchip arrays, on the one hand, and reduced power consumption of modules, on the other. How this is achieved, we will see later, but for now let's turn to the "macroscopic" facts. DDR2 memory modules are produced in a new form factor, in the form of 240-pin DIMMs, which are not electrically compatible with slots for DDR memory modules (by the number of pins, pin spacing, and module pinouts). Thus, the DDR2 standard does not provide for backward compatibility with DDR.

The table below lists the approved naming conventions and specifications for the first three DDR2 standards. It is easy to see that DDR2-400 has the same bandwidth as the current DDR-400 memory type.

The first DDR2 memory modules will ship in 256MB, 512MB and 1GB variants. However, the standard provides for the possibility of building modules of significantly larger capacity up to 4 GB, which, however, are specialized modules (not compatible with desktop options, at least on this moment). In the future, the appearance of modules with even greater capacity is expected.

DDR2 chips will be manufactured using an FBGA (Fine Ball Grid Array) package that is more compact than the traditional TSOP-II variant, allowing for higher chip capacities in a smaller size and improved electrical and thermal performance. This packaging method is already used by some DDR manufacturers as an option, but is recommended for use in terms of the JEDEC standard.

The voltage consumed by DDR2 modules is 1.8 V according to the standard, which is much less compared to the supply voltage of DDR devices (2.5 V). A quite expected (although not so obvious) consequence of this fact is a decrease in power consumption, which is important for manufacturers of both laptops and large workstations and servers, where the problem of power dissipated by memory modules is far from the last place. DDR2 from the inside

The DDR2 standard includes several important changes DDR specifications related to data transfer, which allow you to achieve more high frequencies with lower power consumption. How exactly is the reduction in power dissipation achieved while increasing the speed of the modules, we will consider right now.

Data sampling

The main change in DDR2 is the ability to fetch 4 bits of data per clock at once (4n-prefetch), as opposed to the 2-bit fetch (2n-prefetch) implemented in DDR. In essence, this means that on each clock cycle of the DDR2 memory bus, it transfers 4 bits of information from the logical (internal) banks of the memory chip to the I / O buffers over one data interface line, while the usual DDR is able to transfer only 2 bits per clock per line . Quite naturally, the question arises if this is so, then why is the effective bandwidth of DDR2-400 the same as that of a regular DDR-400 (3.2 GB/s), and not doubled?

To answer this question, let's first look at how conventional DDR-400 memory works. In this case, both the memory core and the I/O buffers operate at a frequency of 200 MHz, and the "effective" frequency of the external data bus, thanks to DDR technology, is 400 MHz. According to the 2n-prefetch rule, at each memory cycle (200 MHz), 2 bits of information enter the I / O buffer on each data interface line. The task of this buffer is multiplexing/demultiplexing (MUX/DEMUX) of the data stream in a simple way, "distillation" of a narrow high-speed stream into a wide low-speed one, and vice versa. Since in a DDR SDRAM memory chip, the logical banks have a data bus width connecting them and a level amplifier twice as wide as from read latches to external interface, the data buffer includes a 2-1 type multiplexer. In general, since memory chips, unlike modules, can have different data bus widths usually x4/x8/x16/x32, the use of such a MUX/DEMUX (2-1) scheme implemented in DDR means that the internal a data stream of width X and frequency Y from the array is converted to an external stream of width X/2 and frequency 2Y. This is called Peak Bandwidth Balance.

Let us now consider the operation diagram of a DDR2 SDRAM memory chip device, equal frequency and “equally wide” (ie the same data bus width) relative to the DDR chip of the DDR-400 memory module. First of all, we note that the width of the external data bus has remained absolutely the same 1 bit/line, as well as its effective frequency (in the considered example 400 MHz). Actually, this is already enough to answer the question posed above why the theoretical memory bandwidth of equal-frequency DDR2 and DDR memory modules are equal to each other. Further, it is obvious that the use of the 2-1 multiplexer used in DDR SDRAM is no longer suitable in the case of DDR2 SDRAM that fetches data according to the 4n-prefetch rule. Instead, it requires the introduction of more complex scheme with additional conversion stage type 4-1 multiplexer. This means that the core output has become four times wider than the external interface of the microcircuit and the same number of times lower in frequency of operation. That is, by analogy with the example discussed above, in the general case, the MUX/DEMUX 4-1 circuit converts an internal data stream of X width and Y frequency from the array to an external X/4 width data stream and 4Y frequency.

Since in this case the core of the memory chips is synchronized at a frequency that is half that of the external one (100 MHz), while in DDR the synchronization of the internal and external data streams occurs at the same frequency (200 MHz), among the advantages of this approach is an increase in the percentage of good chips and reduced energy consumption modules. By the way, this also explains why the DDR2 standard assumes the existence of memory modules with an "effective" frequency of 800 MHz, which is twice as high as the current generation of DDR memory. After all, it is precisely this “effective” DDR2 frequency that can be achieved even now, with DDR-400 memory chips operating at a native frequency of 200 MHz, if data is sampled according to the 4n-prefetch rule according to the scheme discussed above.

Thus, DDR2 means abandoning the extensive way of developing memory chips in the sense of simply further increasing their frequency, which significantly complicates the production of stable working memory modules in large quantities. It is being replaced by an intensive development path associated with the expansion of the internal data bus (which is a mandatory and inevitable solution when using more complex multiplexing). We dare to suggest that in the future it is quite possible to expect the appearance of DDR4 memory, which fetches not 4, but 8 bits of data from memory chips at once (according to the 8n-prefetch rule, using an 8-1 type multiplexer), and working at a frequency no longer 2, but 4 times lower in relation to the frequency of the I / O buffer :). Actually, there is nothing new in this approach this has already been seen in memory chips like Rambus DRAM. However, it is easy to guess that the downside of this development path is the complication of the MUX / DEMUX I / O buffer device, which in the case of DDR2 must serialize four bits of data read in parallel. First of all, this should affect such an important characteristic of memory as its latency, which we will consider below.

On-chip termination

The DDR2 standard also includes a number of other improvements that improve various characteristics of the new type of memory, including electrical ones. One of such innovations is intra-chip signal termination. Its essence lies in the fact that to eliminate excessive electrical noise (due to signal reflection from the end of the line) on the memory bus, resistors are used to load the line not on the motherboard (as was the case with previous generations of memory), but inside the chips themselves. These resistors are deactivated when the chip is in operation and, conversely, are activated as soon as the chip enters the idle state. Since the signal is now damped much closer to its source, this eliminates electrical noise inside the memory chip during data transfer.

By the way, in connection with the technology of on-chip termination, one cannot but dwell on such a moment as ... the heat dissipation of the module, which, in general, the new DDR2 standard is designed to actively reduce in the first place. Indeed, such a signal termination scheme leads to the occurrence of significant static currents inside the memory chips, which leads to their heating. Well, this is true, although we note that the power consumed by the memory subsystem generally, this should not grow at all (just the heat is now dissipated elsewhere). The problem here is a little different namely, the possibility of increasing the frequency of operation of such devices. It is very likely that this is why the first generation of DDR2 memory is not DDR2-800 at all, but only DDR2-400 and DDR2-533, for which the heat dissipation inside the chips remains at an acceptable level so far.

Added Delay

Incremental Latency (also known as "Delayed CAS") is another enhancement introduced to the DDR2 standard that is designed to minimize the instruction scheduler's idle time when transferring data from/to memory. To illustrate this (using a read as an example), let's start with reading Bank Interleave data from a DDR2 device with an additional delay of zero, which is equivalent to reading from conventional DDR memory.

At the first stage, the bank is opened using the ACTIVATE command, along with the supply of the first component of the address (row address), which selects and activates the required bank and the row in its array. During the next cycle, the information is transferred to the internal data bus and sent to the level amplifier. When the amplified signal level reaches the required value (after a time called the delay between determining the address of the row and column, t RCD (RAS-to-CAS Delay), a read command with auto-recharge (READ with Auto-Precharge, RD_AP) can be issued for execution together with column address to select the exact address data to be read from the level amplifier. After the read command is issued, the column select strobe delay t CL (CAS signal delay, CAS Latency) is performed, during which the data selected from the level amplifier is synchronized and transmitted to the external pins of the microcircuit. In this case, a situation may arise when the next command (ACTIVATE) cannot be sent for execution, since the execution of other commands has not yet ended at this point in time. So, in the example under consideration, the activation of the 2nd bank should be delayed by one clock cycle, since at this moment the read with auto-recharging (RD_AP) command from bank 0 is already being executed. Ultimately, this leads to a break in the sequence of data output on the external bus , which reduces the actual memory bandwidth.

To eliminate this situation and increase the efficiency of the instruction scheduler, DDR2 introduces the concept of additional (additional) delay, t AL . If t AL is nonzero, the memory device monitors the READ (RD_AP) and WRITE (WR_AP) commands, but delays their execution for a time equal to the value of the additional delay. Differences in the behavior of a DDR2 memory chip with two different values ​​of t AL are shown in the figure.

The top figure describes the operation mode of the DDR2 chip at t AL = 0, which is equivalent to the operation of the DDR memory chip device; the lower one corresponds to the case t AL = t RCD - 1, standard for DDR2. With this configuration, as can be seen from the figure, the ACTIVATE and READ commands can be executed one after the other. The actual implementation of the READ command will be delayed by the amount of the additional delay, i.e. in reality, it will be executed at the same moment as in the diagram above.

The following figure shows an example of reading data from a DDR2 chip assuming t RCD = 4 cycles, which corresponds to t AL = 3 cycles. In this case, by introducing additional latency, ACTIVATE/RD_AP commands can be executed in succession, in turn allowing data to be output in a continuous manner and maximizing real memory bandwidth.

CAS issuance delay

As we saw above, DDR2, in terms of external bus frequency, operates at higher speeds than DDR SDRAM. At the same time, since the new standard does not imply any significant changes in the technology of manufacturing the chips themselves, static delays at the DRAM device level should remain more or less constant. Typical intrinsic latency for DDR type DRAM devices is 15 ns. For DDR-266 (with a cycle time of 7.5 ns) this is equivalent to two cycles, and for DDR2-533 (cycle time of 3.75 ns) it is equivalent to four.

As the memory frequencies increase further, it is necessary to multiply the number of supported CAS signal output delay values ​​(in the direction of b O higher values). The CAS delays determined by the DDR2 standard are presented in the table. They are in the range of integers from 3 to 5 cycles; the use of fractional delays (multiples of 0.5) is not allowed in the new standard.

The delays of a DRAM device are expressed by the unit of a cycle (t CK), i.e. are equal to the product of the cycle time and the selected delay value CAS (t CL). Typical delay values ​​for DDR2 devices fall within the range of 12-20 ns, on the basis of which the CAS delay value used is selected. Use b O Larger delays are unreasonable due to performance considerations of the memory subsystem, while smaller delays are inappropriate due to the need for stable operation of the memory device.

Write delay

The DDR2 standard also introduces changes to the write delay specification (WRITE commands). Differences in the behavior of the write command in DDR and DDR2 devices are shown in the figure.

DDR SDRAM has a write latency of 1 cycle. This means that the DRAM device starts "capturing" information on the data bus, on average, one clock cycle after the WRITE command arrives. However, given the increased speed of DDR2 devices, this period of time is too short for the DRAM device (namely, its I/O buffer) to successfully prepare to "capture" data. In this regard, the DDR2 standard defines write latency as the delay in issuing CAS minus 1 cycle (t WL = t CL - 1). It is noted that linking the WRITE delay to the CAS delay not only allows you to achieve higher frequencies, but also simplifies the synchronization of read and write commands (setting Read-to-Write timings).

Recovery after recording

The procedure for writing to SDRAM memory is similar to a read operation with a difference in the additional interval t WR , which characterizes the recovery period of the interface after the operation (usually this is a two-cycle delay between the end of data output to the bus and the initiation of a new cycle). This time interval, measured from the end of the write operation to the moment it enters the regeneration stage (Auto Precharge), ensures the restoration of the interface after the write operation and guarantees the correctness of its execution. Note that the DDR2 standard does not change the write recovery period specification.

Thus, the delays of DDR2 devices in general can be considered one of the few characteristics in which the new standard loses to the DDR specifications. In this connection, it is quite obvious that the use of equal-frequency DDR2 is unlikely to have any advantages in terms of speed in relation to DDR. How it really is as always, the results of the relevant tests will show. Test results in RightMark Memory Analyzer

Well, it's time to move on to the test results obtained in the version 3.1 test package. Recall that the main advantages of this test in relation to other available memory tests are its wide functionality, openness of the methodology (the test is available to everyone for review in the form), and carefully designed documentation.

Test bench and software configurations

Test stand #1

• Processor: Intel Pentium 4 3.4 GHz (Prescott core, Socket 478, FSB 800/HT, 1 MB L2) at 2.8 GHz
• Motherboard: ASUS P4C800 Deluxe on Intel chipset 875P
• Memory: 2x512 MB PC3200 DDR SDRAM DIMM TwinMOS (timings 2.5-3-3-6)

Test stand #2

• Processor: Intel Pentium 4 3.4 GHz (Prescott core, Socket 775, FSB 800/HT, 1 MB L2) at 2.8 GHz
• Motherboard: Intel D915PCY based on Intel 915 chipset
• Memory: 2x512 MB PC2-4300 DDR2 SDRAM DIMM Samsung (4-4-4-8 timings)

Software

• Windows XP Professional SP1
• Intel Chipset Installation Utility 5.0.2.1003

Maximum real memory bandwidth

The measurement of the maximum real memory bandwidth was carried out using the subtest Memory Bandwidth, presets Maximal RAM Bandwidth, Software Prefetch, MMX/SSE/SSE2. As the name of the selected presets suggests, this series of measurements uses the standard method of optimizing read operations from memory Software Prefetch, the essence of which is to pre-fetch data that will be required later from RAM to the L2 cache of the processor. To optimize memory writes, the Non-Temporal Store method is used to avoid cache clogging. The results using the MMX, SSE and SSE2 registers turned out to be almost identical for example, below is a picture obtained on the Prescott/DDR2 platform using SSE2.

Prescott/DDR2, maximum real memory bandwidth

Note that there are no significant qualitative differences between DDR and DDR2 on equal frequency Prescotts in this test. But what is more interesting is that quantitative characteristics The memory bandwidth of DDR-400 and DDR2-533 are very close! (see table). And this is despite the fact that DDR2-533 memory has a maximum theoretical memory bandwidth of 8.6 GB/s (in dual-channel mode). Actually, we do not see anything surprising in the result obtained, because the processor bus is still 800 MHz Quad-Pumped Bus, and its bandwidth is 6.4 GB/s, so it is the limiting factor.

With regard to the efficiency of write operations, with respect to reading it is easy to see that it has remained the same. However, this again looks quite natural, since in this case the write bandwidth limit (2/3 of the read bandwidth) is explicitly set by the microarchitectural features of the Prescott processor.

Memory latency

First of all, let's take a closer look at how and why we measured the "true" memory latency, since measuring it on Pentium 4 platforms is actually far from a trivial task. And this is due to the fact that the processors of this family, in particular, the new Prescott core, are characterized by the presence of a rather "advanced" asynchronous hardware data prefetcher, which makes it very difficult to objectively measure this characteristic of the memory subsystem. Obviously, the use of sequential memory bypass methods (forward or reverse) to measure its latency is completely unsuitable in this case the Hardware Prefetch algorithm in this case works with maximum efficiency, “masking” latencies. The use of random bypass modes is much more justified, however, a truly random memory bypass has another significant drawback. The fact is that such a measurement is performed under conditions of almost 100% D-TLB miss, and this introduces significant additional delays, which we already wrote about. Therefore, the only possible option (among the methods implemented in RMMA) is pseudo-random a memory traversal mode in which the loading of each subsequent page is linear (nullifying D-TLB misses), while the traversal within the memory page itself is truly random.

Nevertheless, the results of our past measurements have shown that even such a measurement technique underestimates the latency values ​​quite a lot. We believe that this is due to another feature of the Pentium 4 processors, namely, the ability to “capture” two 64-byte lines from memory to the L2 cache at once with each access to it. To demonstrate this phenomenon, the figure below shows the curves of the dependence of the latency of two consecutive accesses to the same memory line on the offset of the second element of the line relative to the first, obtained on the Prescott / DDR2 platform using the test D-Cache Arrival, preset L2 D-Cache Line Size Determination.

Prescott/DDR2, data arrival via L2-RAM bus

It can be seen from them (the random walk curve is the most indicative) that access to the second element of the line is not accompanied by any additional delays up to 60 bytes inclusive (which corresponds to the true size of the L2 cache line, 64 bytes). The area 64-124 bytes corresponds to reading data from the next line of memory. Since the latency values ​​in this area increase only slightly, this means that the next line of memory is really "pumped" into the L2 cache of the processor immediately after the requested one. What can be done from all this practical conclusion? The most direct one: in order to "deceive" this feature of the Hardware Prefetch algorithm, which works in all cases of memory bypass, it is enough to simply bypass the chain with a step equal to the so-called "effective" length of the L2 cache line, which in our case is 128 bytes.

So, let's go directly to the results of latency measurements. For clarity, here are the L2-RAM bus unloading graphs obtained on the Prescott/DDR2 platform.

Prescott/DDR2, memory latency, line length 64 bytes

Prescott/DDR2, memory latency, line length 128 bytes

As in the case of real memory bandwidth tests, the latency curves on another platform Prescott/DDR look exactly the same on a qualitative level. Only the quantitative characteristics differ somewhat. It's time to contact them.

* latency in the absence of unloading of the L2-RAM bus

It is easy to see that the latency of DDR2-533 turned out to be higher than that of DDR-400. However, there is nothing supernatural here according to the above theoretical foundations new DDR2 memory standard, that's the way it should be.

The difference in latency between DDR and DDR2 is almost imperceptible with a standard 64-byte memory bypass (3 ns in favor of DDR) when the hardware prefetcher is actively working, however, with a "two-line" (128-byte) chain bypass, it becomes much more noticeable. Namely, the DDR2 latency minimum (55.0 ns) is equal to the DDR latency maximum; if we compare the minimum and maximum latencies with each other, the difference is about 7-9 ns (15-16%) in favor of DDR. At the same time, it must be said, the practically equal values ​​of the “average” latency obtained in the absence of L2-RAM bus offload are somewhat surprising, both in the case of a 64-byte bypass (with a data prefetch) and a 128-byte bypass (without it). ). Conclusion

The main conclusion that suggests itself on the basis of the results of the first comparative testing DDR and DDR2 memory general view can be formulated as follows: "the time for DDR2 has not yet come." The main reason is that it is pointless to fight for increasing the theoretical memory bandwidth by increasing the frequency of the external memory bus. After all, the bus of the current generation of processors still operates at a frequency of 800 MHz, which limits the real throughput of the memory subsystem at the level of 6.4 GB/s. And this means that at present it makes no sense to install memory modules with a higher theoretical bandwidth, since the currently existing and widely used DDR-400 memory in dual-channel mode fully justifies itself, and, in addition, has lower latency. By the way, about the last one, an increase in the frequency of the external memory bus is inevitably associated with the need to introduce additional delays, which, in fact, is confirmed by the results of our tests. Thus, we can assume that the use of DDR2 will justify itself at least not earlier than the moment when the first processors with a bus frequency of 1066 MHz and higher appear, which will make it possible to overcome the limitation imposed by the speed of the processor bus on the real bandwidth of the memory subsystem as a whole.